The invention relates to an electrical circuit arrangement comprising a plurality of circuit units connected to a common path and to an electrical circuit unit for use in such an electrical circuit arrangement.
One problem is designing and constructing electronic systems which include a plurality of circuit units is the assignment to each circuit unit of a unique identity or address. Such circuit units may be RAMs, ROMs, Codecs, etc. which may be, for example, in the form of integrated circuits, hybrid circuits or printed circuit boards carrying a plurality of discrete and/or integrated circuits. One possibility is to assign an address to each circuit unit at the manufacturing state, but this leads both to more expensive circuit units and to a greater possibility of inserting the circuit units into the wrong position within the system. Another possibility is to provide each circuit unit with a number of programming pins which are connected to internal decoding circuitry and to external potentials either directly or through switches. These two possibilities may be combined so that part of the address is fixed at the manufacturing stage and part is programmable. The fixed portion of the address normally indicates the type of circuit, i.e. RAM, Codec, etc., while the programmable part identifies the particular circuit of that type. This reduces the number of external pins required which is particularly important when the circuit unit is formed as an integrated circuit since the cost of an integrated circuit increases significantly with each additional pin provided. However the number of circuit units which can be addressed is limited if the number of programming pins is not to become excessive. A further possibility is to provide an external address decoding circuit feeding an enable pin on the integrated circuit. This reduces the number of addressing pins required to one but has the disadvantage that additional circuit elements have to be provided to enable addressing to be effected thus increasing the cost and complexity of the system.
When the circuit units are formed as printed circuit boards (PCBs) which are plugged into either a mother board or a wiring frame it is usual to provide programming switches on the PCB which are appropriately set to give the PCB address. This arrangement has a number of disadvantages amongst which are the difficulties involved with mounting and soldering the switches to the PCB, the possibility of incorrectly setting the switches, and the area of the PCB occupied by the switches which reduces the available board area for the functional parts of the circuit unit.
U.K. Patent Specification No. 1295332 discloses an electrical circuit arrangement and an electrical circuit unit as set forth in the first and second paragraphs. The description with reference to FIGS. 6 and 7 of that specification shows a circuit arrangement comprising a plurality of terminals arranged along a transmission line at approximately 10 meter intervals. Each terminal includes an address generator which is incremented by a clock signal applied thereto via a gate which is opened and closed by a start and a stop signal transmitted along the transmission line. Each terminal is provided with a high frequency (10 MHz) clock signal generator. By using the signal propagation delay along the transmission line and ensuring a minimum spacing between terminals a difference in time of opening of the gate in each terminal can be achieved such that the difference is greater than the period of the clock signal. Hence each address generator will provide a different address. This circuit arrangement may be satisfactory where a large spacing between terminals is possible, though it may also impose stringent requirements on the clock signal generators, but is impracticable when the terminals are separated by small distances since the required clock frequency would be correspondingly increased.
U.S. Pat. No. 4,458,357 discloses apparatus for automatically producing a unique identification code (or address) for a number of circuit boards in an electronic system. Each circuit board includes a counter to which the system clock is applied, the counter also having an inhibit input to which a signal may be applied to prevent the counter from counting. Initially all the counters are inhibited and a system rest signal presets all the counters to a maximum count. The counter on the first board is then enabled and starts to count down. As soon as the count changes an enable signal is transferred to the next board. This process is continued until the counter on the final board is enabled and changes count when a disable signal is generated and applied to all the counters simultaneously. Thus all the boards are allocated a unique address, the first board having the lowest numbered address, but the actual address will depend on the number of boards present.
A disadvantage of this arrangement is that an external connection to each board is required for both the counter enable and disable signals. Also two conductors are required on the mother board connecting the circuit boards. The number of pins on each circuit board and available area on mother boards for the circuit board interconnections is frequently limited.
It is an object of the invention to overcome the disadvantages of the prior art systems disclosed in U.K. Patent No. 1295332 and U.S. Pat. No. 4,458,357.
It is a further object of the invention to reduce the number of interconnections required between the circuit units.